Kalpana Suryawanshi

About Kalpana Suryawanshi

Rich experience from conception to completion in various areas of semiconductor industry, including Digital IP Designs, SOC chip implementation [from spec definition to tape out], verification, digital layout, timing closure, Post silicon support.• Mentored many leads and engineers across various functions. Seeded and grown technically strong team from scratch, small to large size technical teams.• Lead and successfully delivered 20+ SoC IC related to these end markets - Micro controller, Motor Drives, Wireless baseband, wireless connectivity and GPS.• Specialized in coming up with Power, Area and performance optimized die.• Deeply involved in strategy planning, contributed to product line roadmap definition. • Delivered several strategic, best in class technological solutions including design of CPU subsystem, AHB/AXI interconnects, DMA and memory controller, System Power, reset and clock controller, low cost PWM generator, various smart hardware based controller for stepper and BDC motor control application.• Achieved various Efficiency vectors like early stage power, area and effort estimation, Annual resource planning, predictable execution schedules, first time Silicon success, efficiency improvement via automation, Integration of AI into design flow.

Experience

1. Chip Design Manager - Microcontroller

   Texas Instruments

   Jan 2023 — Present · Bengaluru, IN

Education

• SGSITS Indore

  Engineerong, Computer Science

  1994 — 1997

• Indian Institute of Technology, Kharagpur

  Mtech, ELECTRONICS

  1998 — 2000

Skills

• Verilog
• Fpga
• Asic
• Mixed Signal
• System on a Chip (Soc)
• Semiconductors
• Debugging
• Hw/Sw Integration
• Logic Synthesis
• Ip
• Amba Ahb
• Soc
• Low-Power Design
• Rtl Design
• Static Timing Analysis
• Application-Specific Integrated Circuits (Asic)
• Wireless
• Embedded Systems
• Eda
• Microcontrollers
• Integrated Circuits (Ic)
• Integration
• Rtl Coding
• Ic
• Vlsi
• Systemverilog