Kalaiselvan Rajasekaran
Aspiring Design Verification Engineer\\nVerilog | SV | UVM
- Role
- Associate Software Engineer at Bosch Global Software Technologies
- Location
- Vellore, IN
- LinkedIn followers
- 500 followers
About Kalaiselvan Rajasekaran
An undergraduate student in Electronics, aspiring to work and seeking opportunities in Design Verification domain in VLSI. Technical Proficiencies Include: HDL: Verilog HVL: SystemVerilog VERIFICATION METHODOLOGY: Constraint Random Coverage Driven-Verification | Assertion Based Verification - SVA TB Methodology: UVM( Universal Verification Methodology) EDA TOOLS: Mentor Graphics-Questasim, Modelsim, Altera Quartus Prime, Xilinx Vivado. DOMAIN: ASIC/FPGA front-end Design and Verification Protocols : I2C, UART, SPI, APB. PROGRAMMING LANGUAGES: C, C++,Python OPERATING SYSTEMS: Windows, UNIX CORE SKILLS:[RTL Coding using Synthesizable constructs of Verilog | FSM based design Simulation | Functional Coverage | Static Timing Analysis | Assertion Based Verification using System Verilog Assertions]
Experience
Associate Software Engineer
Bosch Global Software Technologies
Jan 2024 — Present · Coimbatore, IN
Education
Vellore Institute of Technology
Master of Technology - MTech
2025 — 2027
Shanmugha Arts, Science, Technology & Reserch Academy (SASTRA), Thanjavur
Btech Electronics and instrumentation
2019 — 2023
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