Kalai Rajah N
Dv @NVIDIA
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WORK HISTORY
Dv @NVIDIA
San Francisco, CA, US
EDUCATION
The University of Texas at Dallas
MS, Electrical Engineering
University of Madras
BE, Electronics and Communication Engineering
The University of Texas at Dallas
MS, Computer Engineering
SKILLS
ABOUT KALAI RAJAH N
Hands on experience in- Memory Subsystem verification - Out-of-Order Memory Management Unit(MMU) blocks- Full chip/Top level co-simulation checker environment- UVM methodology flow /setup- Verification Infrastructure- Block level/system level verification environments spread across multiple processor architectures/ARM Coresight architecture- Functional verification, debug, coverage, verification environment, directed and random testing- BIOS, x86 microcode, random/directed stimulus, checkers, virtualization, power management features- Diagnostic software for caches/TLBs in x86/SPARC processors. Extensive programming using C, x86/SPARC assembly on Solaris and Linux platforms. Strong exposure to Operating Systems, computer architecture and x86 /MIPS/ARMv8/RISC-V.Familiarity with network protocols, network programming, storage networks.Specialties: Functional verificationComputer ArchitectureSystemVerilog, UVM, VMMProcessor Micro-architecture (x86, SPARC, MIPS,ARM v7/v8/RISC-V)ARM Debug(Coresight).Power Management
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