Kajal Zatale

About Kajal Zatale

I am Kajal, currently working for Intel Corp as a SoC Design Engineer for a memory controller ASIC. It has been approx 5 years since I joined Intel and have worked on multiple aspects of a design cycle. My area of expertise lies around implementing RTL for design features by having a good discussion with my architects. I have worked on multiple full-chip Synopsys flows like VCS, Spyglass lint, recently studied Fusion compiler for future project work and VC_LP. Moreover, I have a good background of writing UPF from the specified power intent and setting up/running VC_STATIC flows over the RTL and netlist. My strengths are perseverance for new-learning/opportunity, risk-taking for better performance, fearless communication skills and team-work.

Experience

1. Staff Design Engineer

   高通

   May 2023 — Present · San Diego, CA, US

Education

• Portland State University

  Master of Science (M.S.)

  2015 — 2017

• Sant Gadge Baba Amravati University

  Bachelor of Engineering (B.E.)

  2010 — 2014

Skills

• Leadership
• Red Hat Linux
• Python
• Public Speaking
• Modelsim
• Static Timing Analysis
• Rtl Design
• Logic Synthesis
• Microsoft Office
• Matlab
• Fpga Synthesis
• Perl
• Functional Verification
• Cadence Virtuoso
• Vhdl
• C
• Verilog
• C++
• Fpga Synthesis
• Logic Design