Kaibin Ji
ASIC Design Engineer at Apple
- Role
- Asic Ip Design Engineer at Apple
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Asic Ip Design Engineer
May 2017 — Present · San Francisco, CA, US
Education
University of Liverpool
Bachelor of Engineering (B.Eng.), Electronic Engineering
2013 — 2015
Xi'an Jiaotong-Liverpool University
Bachelor of Engineering (BEng), Electronic Science and Technology
2011 — 2013
University of Southern California
Master of Science (M.S.), VLSI Design
2015 — 2017
Skills
- Microcontrollers
- C
- Field-Programmable Gate Arrays (Fpga)
- Perl
- Systemverilog
- Verilog
- Matlab
- Vhdl
- Computer Architecture
- Modelsim
- C++
- Cadence Virtuoso
- Arm Cortex-M
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