Kabilesh I
Physical Design | Analog Layout | Physical Verification | RTL | Bachelor’s in Electrical and Electronic Engineering
- Role
- Analog Layout at Capgemini Engineering
- Location
- Coimbatore, TN, IN
- LinkedIn followers
- 500 followers
About Kabilesh I
I\'m passionate about VLSI design with hands-on experience in the Physical Design (PnR) flow, along with signoff flows including PrimeTime for STA.> Gained Hands-on experience in transistor-level analog layout for 3nm FinFET blocks. Executed custom placement & routing of critical analog circuits using Cadence Virtuoso, applying matching and isolation techniques (guard rings), with physical verification using Calibre.> Worked on Physical Verification phase, 7nm, 5nm, clearing DRCs, performing LVS checks, handling antenna and density violations.> In addition to Physical Design, I possess experience in RTL design using Verilog, where I developed a router 1x3.> Activities include automation using TCL, Perl, Unix shell scripting and Python, helping to optimise and generate reports.
Experience
Analog Layout
Aug 2025 — Present · Coimbatore, IN
Worked on 3nm transistor-level custom analog layout. Implemented transistor placement, routing, shielding, power mesh creations. Perfomed guard ring placement, dummy device insertion. Achieved lvs, drc clean.
Education
Sona College of Technology
Bachelor of Engineering - BE, Electrical and Electronics Engineering
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