K Saikiran
Physical verification engineer at Capgemini
- Role
- Physical Verification Engineering at Capgemini Engineering
- Location
- Hyderabad, IN
- LinkedIn followers
- 500 followers
About K Saikiran
Profficient in physical verification experience on 7nm, 10nm, 5nm and 18A Implemented timing & functional ECO\'s and buffer insertions,upsizing/down sizing a cell,net improvement and degradation Experienced in layout techniques to mitigate RV,EM,IR, crosstalk violation as part of ECO Shielding for critical nets by ground to avoid crosstalk/signal Integrity problem Implemented scripts that tackle DRC issues and crafting GUI utilities to enhance efficiency in manual processes. Good understanding of block-level, subsystem-level, and full-chip Physical Verification. Good hands on experience in full-chip Physical Verification checks, covering DRC, Antenna, and Density. From floorplan conception to signoff, I\'ve overseen subsystems for PV closure. Handled blocks of various complexities and congestion Provided guidance to Physical Design engineers, ensuring the resolution of Physical Verification issues and the seamless convergence of blocks. My hands-on experience extends to addressing layout PV issues and collaborating closely with block owners for systematic issue rectification through scripts and manual fixes. Responsible for sign off check clean before the tape out
Experience
Physical Verification Engineering
Mar 2022 — Present · Bengaluru, IN
Education
SREYAS INSTITUTE OF ENGINEERING & TECHNOLOGY
Bachelor of Technology - BTech
2017 — 2021
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