Jyothishri G R
Lead Design Engineer at Cadence Design Systems
- Role
- Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Jyothishri G R
Experience in the field of Circuit Design, IR/EM analysis, Verilog Modelling and Characterisation of IO cells (.libs). Enthusiastic engineering professional with a Master\'s Degree focused in VLSI Design from Vellore Institute of Technology.
Experience
Design Engineer
Jan 2018 — Present · Bengaluru, IN
Schematic Design of POC, Voltage Reference generator, Perform various Performance and Reliability checks across PVT.• Responsible for analysis of Electro-migration and IR drop for DDRIO high speed circuits of Advanced Process nodes.• Developing customized process automation solutions for design flow procedures using Shell Scripting
Education
Vellore Institute of Technology
Master's Degree, VLSI Design
2013 — 2015
Skills
- Verilog
- Cadence Virtuoso
- Tickel
- Charaterisation
- Linux
- Modelsim
- C
- Microsoft Office
- Cadence Encounter
- Cadence Spectre
- Perl
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