Jyothi B Amarnadh Velamala

Design Engineering Architect

Role: Design Engineering Architect at Cadence
Location: Austin, TX, US
LinkedIn followers: 500 followers

EngineeringView LinkedIn profile

Experience

Design Engineering Architect
Cadence
Mar 2025 — Present · Austin, TX, US
Design Technology Cooptimization (DTCO) and working on foundry engagements

Education

Arizona State University
Doctor of Philosophy (Ph.D.)
2010 — 2012
Arizona State University
Master of Science (M.S.)
2008 — 2010
Indian Institute of Technology, Guwahati
B Tech
2004 — 2008

Skills

Tcl
Analog
Static Timing Analysis
Tcad
Perl
Reliability
Cmos
Simulations
Very-Large-Scale Integration (Vlsi)
Analog Circuit Design
Characterization
Vlsi
Matlab
Integrated Circuit Design
Asic
C
Ic
Mixed Signal
Semiconductor Device
Semiconductor Failure Analysis
Spice

Contact information

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Work email
•••••@cadence.com
Personal email
•••••@•••••.com
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Current company

Cadence Design Systems

12K employees · San Jose, California, United States

Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.

cadence.com

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