Junna Raju
Trained VLSI Fresher | ECE Graduate | RTL Design & Verification | Digital Electronics | Verilog | SystemVerilog | UVM | Assertions | Functional Coverage |Debugging | QuestaSim
- Role
- Design and Verification at Vlsi First
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Junna Raju
Iam Junna Raju, a passionate VLSI Design and Verification Engineer with a solid foundation in Electronics and Communication Engineering (ECE), earned through my B.Tech from J.B.Institute Of Engineering And Technology College. Throughout my academic career, I developed a deep understanding of digital electronics and Verilog HDL, which laid the groundwork for my journey into VLSI. In addition to my coursework, Driven by my passion for VLSI, I am eager to continuously expand my skill set, particularly in areas such as SystemVerilog, UVM, and assertion-based verification techniques. I am currently undergoing training at VLSI FIRST, where I am honing my abilities in design and verification methodologies. I thrive in collaborative environments and look forward to contributing to innovative projects alongside professionals who share my enthusiasm for cutting-edge technology. My goal is to leverage my knowledge and experience to contribute meaningfully to the semiconductor industry, while constantly seeking new challenges to grow and evolve as a Design and Verification Engineer.
Experience
Design and Verification
May 2025 — Present · Hyderabad, IN
Education
Harikrishna high school
Tenth class
Narayana Junior College - India
MPC
J.B.Institute of Engineering & Technology
Bachelor of Technology - BTech, Electronics and Communications Engineering
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