Jungwon Kim
Product Engineer/Fail Analysis expert across Memory/CPU products.
- Role
- Dram Customer Quality - Senior Manager at Samsung Semiconductor
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Jungwon Kim
Core Competences. DRAM/3D XPoint Memory Cell Characterization, Si-interposer. Fail Mechanism/Test Contents/Yield Analysis development for DRAM/CPU. Photon Emission/OBIRCH/Sample prep/SEM/FIB/Nano-Probing/Parametric analyzer. ATE(Advantest, Teradyne), Bench tester(Micron u-Mate, Intel HDMT), Boundary SCAN. Circuit Analysis with Layout/Schematic tool(Cadence, Synopsys), Yield Exploer(Synopsys). Python, JMP script - Data log/Fail bitmap analysis
Experience
Dram Customer Quality - Senior Manager
Dec 2025 — Present · San Jose, CA, US
Quality management for Tier 1 customer.
Education
Kyung Hee University
BE, Electronics
1989 — 1994
Skills
- Jmp
- Asic
- Failure Analysis
- Semiconductor Industry
- Verilog
- Semiconductors
- Ic
- Electronics
- Product Engineering
- Testing
- Silicon
- Yield
- Soc
- R&D
- Flash Memory
- Characterization
- Dram
- Test Engineering
- Cmos
- Integrated Circuits (Ic)
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