Jungbae Lee
Packaging Engineer at Texas Instruments
- Role
- Packaging Engineer at Texas Instruments
- Location
- Dallas, TX, US
- LinkedIn followers
- 500 followers
About Jungbae Lee
Semiconductor packaging process development engineer with over 13 years of experience, specializing in advanced packaging technologies such as FCBGA, FCCSP, 2.5D/3D TSV for Analog and Memory devices.Proven expertise in hybrid bonding die stacking, TC bonding, Flip chip attach and yield-driven process optimization. Process & Equipment Innovation • Deep involvement in HBM, DRAM, mNAND, 2.5D/3D TSV, FCBGA, FCCSP for next-gen IC packaging. • Expertise in equipment, material, and process development to meet quality, reliability, and cost goals. • Skilled in problem solving, yield improvement, and pathfinding for cutting-edge packaging solutions. Project & Technical Leadership • Managed cross-functional projects on flip chip, underfill, molding and hybrid bonding process optimization. • Experienced in OSAT collaboration and manufacturing scaling.
Experience
Packaging Engineer
Nov 2025 — Present · Dallas, TX, US
Leading FCCSP, FCBGA, and 2.5D packaging development for Analog Devices’ next generation products.* Enable 5nm and 8nm tech node wafer in analog devices- Establishing Substrate roadmap for supply chain and technology strategies- Driving innovation in process design, yield improvement, and technical challenge resolution to support advanced semiconductor integration.
Education
Yonsei University
Master's degree, Material science and Engineering
2011 — 2013
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