Pratik J
Principal Design Engineer at Cadence Design Systems
- Role
- Principal Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Pratik J
Experienced Principal Design Engineer with a demonstrated history of working in the Semiconductor industry. Strong engineering professional skilled in Design Rule Checking (DRC), Phase-Locked Loop (PLL), Caliber, Analog Circuit Design, and CMOS.
Experience
Principal Design Engineer
Jun 2021 — Present
14+ years of experience in VLSI physical design implementation with deep submicron technologies• Worked closely with design team for optimal layout in terms of power, area and performance.4
Education
Visvesvaraya Technological University
Bachelor of Engineering - BE, Electronics and Communications Engineering
2005 — 2009
Skills
- Cmos
- Analog
- Analog Layout
- Cadence Virtuoso
- Design Rule Checking (Drc)
- Integrated Circuit Design
- Caliber
- Mixed Signal
- Eda
- Very-Large-Scale Integration (Vlsi)
- Lvs
- Ic
- Laker
- Layout Versus Schematic (Lvs)
- Vlsi
- Semiconductors
- Pvs
- Virtuoso
- Asic
- Pll
- Mipi
- Drc
- Team Management
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