Joydeep Saha

About Joydeep Saha

Logic design engineer for next generation Media/Camera Hardware IP. Responsible for RTL design and constrained random verification of unit level designs for Media IP. • RTL coding(structural) and testbench validation performed for Cache implementation where requestor is out of order but return on a cache hit is inorder. Direct mapped cache as well as full associative cache(using CAM search)• RTL coding(structural) and testbench validation for 2nd level arbiter design on the input side which has standard credit release interface and 2 FIFOs. Familiar with dv-hold and put-credit release interfaces. • DPI based checker implementation for interfacing System Verilog and C functions.• Validated 3 functional unit blocks in a DUT with random inject testbench from scratch and cleaned the design resulting in 0 bug findings during validation.• Code, branch, toggle and functional Coverage for those RTL units and achieved more than 90% coverage using random inject. Detected missing test cases and incorporated changes in testbench to hit those cases.• Synthesized units for every small design change to check for any timing violations with focus on gate count reduction.• Schmoo based regressions and validation for signals with dv and data alignment which exists at unit boundary.• Debugging RTL2RTL mismatches using jasper goldResponsible for integration of unit level module in SoC and solving clock and reset domain crossing challenges.• Bundle integrity check, smart repeater insertion and Boundary optimization analysis.•Experienced in RTL coding and design using System Verilog, Pre silicon Verification.•Experienced in C++, C,Python and developed the scripts to automate the testing process.•Working knowledge on Windows and Unix Operating systems.•Advance Course Work in CPU architecture, Microprocessor System Design, Low Power Design.Perform functional verification of design on block and system level.Perform synthesis and timing closure.

Experience

1. Senior Engineer

   NVIDIA

   Jan 2025 — Present · Austin, TX, US

Education

• Institute of Engineering & Management

  Bachelor of Technology, Electronics and Communication Engineering

• University of Southern California

  Master of Science (MS), Electrical Engineering

• Institute of Engineering and Management

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

• University of Southern California

  Master's degree, Electrical and Electronics Engineering

  2013 — 2015

• West Bengal University of Technology, Kolkata

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

• St. Mary’s Orphanage and Day School

  Class X secondary education from ICSE, Science

Skills

• C++
• Html
• Cadence Virtuoso
• Microprocessors
• Digital Signal Processors
• Analog Circuit Design
• Java
• Python
• Vlsi
• Algorithms
• Circuit Design
• Verilog
• Pspice
• Matlab
• C
• Perl
• Linux
• Modelsim
• Logic Design
• Assembly Language
• Jsp
• Core Java
• Testing
• Vhdl
• Operating Systems
• Computer Architecture
• Unix
• Rtl Design
• Hardware
• Asic