Joshua Carroccia

Hardware Test Engineer - Nextest Npi Pilot Team @Teradyne

Santa Clara, CA, US
MOBILE NUMBERS
+91 *********19

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WORK HISTORY

Mar 2025 — Present

Hardware Test Engineer - Nextest Npi Pilot Team @Teradyne

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San Jose, CA, US

Define and implement manufacturing test strategies for PCB hardware in semiconductor manufacturing, optimizing test setups and processes with Design and Product Engineering.• Qualify and optimize test fixtures, equipment, and software at the Pilot line and Contract Manufacturer (CM) sites to ensure seamless production.• Investigate and troubleshoot yield issues in PCB hardware during prototype and production builds to improve manufacturing efficiency.• Develop training materials, test station procedures, and troubleshooting guides to support CM teams in semiconductor manufacturing.

EDUCATION

2018 — 2022

University of Windsor

Bachelor of Applied Science - BASc

ABOUT JOSHUA CARROCCIA

Hi, I\'m Josh! I’m a graduate of the Electrical and Computer Engineering program at the…

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Joshua Carroccia — Hardware Test Engineer - Nextest Npi Pilot Team at Teradyne in Santa Clara, CA, US | Unifers