Joshua Tan
- Role
- Amd at Altera
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
Experience
Amd
Present
Skills
- Functional Verification
- Fpga
- Rtl Design
- Ddr3
- Mixed Signal
- Ic
- Analog Circuit Design
- Pcie
- Altera
- Eda
- Integrated Circuits (Ic)
- Processors
- Soc
- Complex Programmable Logic Device (Cpld)
- Debugging
- Xilinx
- Modelsim
- Semiconductors
- Tcl
- Application-Specific Integrated Circuits (Asic)
- Cpld
- Integrated Circuit Design
- Asic
- Static Timing Analysis
- Systemverilog
- System on a Chip (Soc)
- Verilog
- Field-Programmable Gate Arrays (Fpga)
- Signal Integrity
- Hardware Architecture
- Serdes
- Timing Closure
- Digital Signal Processors
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