Joshua Smith
Senior Principal RISC-V Core Designer at SiFive
- Role
- Senior Principal Risc-v Core Designer at SiFive
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
Experience
Senior Principal Risc-v Core Designer
Apr 2018 — Present · San Mateo, CA, US
Lead micro-architect and RTL designer of SiFive\'s P550, P670, and P870 RISC-V cores, SiFive\'s out-of-order cores. Lead designer and responsible for- Instruction fetch and branch prediction units- Rename, dispatch, and retire units- Integer and floating point scheduling
Education
University of Michigan
MSE, Computer Science Engineering
2009 — 2010
University of Michigan
BSE, Computer Engineering
2005 — 2009
Skills
- Debugging
- Rtl Design
- Microarchitecture
- Arm
- C
- Microprocessors
- Simulations
- Computer Architecture
- Functional Verification
- Verilog
- Computer Engineering
- Embedded Software
- Asic
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