Joseph Cesana

Nearly 40 years immersed in research and development, constantly traveling from conference rooms to hotel rooms around the globe, Time to shift my focus and embrace new perspectives.

Role
- É at Intel
Location
Palo Alto, CA, US
LinkedIn followers
500 followers

About Joseph Cesana

RESEARCH & DEVELOPMENT - SoC Leading product development from concept to mass…

Experience

  1. - É

    Intel

    Present

Skills

  • Team Building
  • Verilog
  • Soc
  • Mixed Signal
  • Program Management
  • Hardware Architecture
  • Eda
  • Rtl Design
  • Integrated Circuits (Ic)
  • Silicon
  • Embedded Systems
  • Digital Tv
  • Ic
  • Analog
  • Very-Large-Scale Integration (Vlsi)
  • Set Top Box
  • Video
  • Firmware
  • Mips
  • Asic
  • System on a Chip (Soc)
  • Cross-Functional Team Leadership
  • Arm
  • Processors
  • Image Processing
  • Vlsi
  • Consumer Electronics
  • Semiconductors
  • Microprocessors
  • Fpga
  • Digital Signal Processors
  • Integrated Circuit Design
  • Low-Power Design
  • Debugging
  • Engineering Management
  • System Architecture
  • Field-Programmable Gate Arrays (Fpga)

Find verified contacts for anyone on LinkedIn

Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.

Free plan included · No credit card required

This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.

Joseph Cesana — - É at Intel in Palo Alto, CA, US | Unifers