Joselyn Lopez Bonilla
FPGA Engineer @Draper | Dartmouth\'22 Thayer\'23
- Role
- Fpga Engineer at Draper
- Location
- Cambridge, MA, US
- LinkedIn followers
- 500 followers
About Joselyn Lopez Bonilla
I am a digital hardware engineer with three years of experience in ASIC and FPGA development, currently working at Draper as an FPGA Engineer. I hold a Bachelor of Engineering in Computer Engineering from the Thayer School of Engineering at Dartmouth College. My experience spans formal verification (including equivalence checking and model checking using SystemVerilog Assertions), Verilog/VHDL design, and DFT techniques such as boundary scan and MBIST.
Experience
Fpga Engineer
May 2025 — Present · Cambridge, MA, US
Education
Thayer School of Engineering at Dartmouth
Bachelor of Engineering - BE, Computer Engineering
Dartmouth College
Bachelor of Arts - BA, Engineering Sciences
High School for Public Service-Heroes of Tomorrow
High School Diploma
2014 — 2018
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