Jorge Paredes
Senior Package Layout Engineer en NVIDIA
- Role
- Package Layout Engineering Manager at NVIDIA
- Location
- Fremont, CA, US
- LinkedIn followers
- 500 followers
About Jorge Paredes
I have been working in the design of PCB Layout since 2005, I know how to use different softwares for the design of PCBs (Zuken, Mentor Graphics Expedition, Pads, Orcad Cadence, Altium,etc). I have experience on high speed design and Design for Manufacturability guidelines. I have experience in designing for EMC compliance.Specialties: EMC knowledge, High Speed design, Design for Manufacturability, IPC standards, PHP, MySQL, VBA, VB.Net
Experience
Package Layout Engineering Manager
Aug 2024 — Present · US
Education
Tecnológico de Monterrey
Engineer, Electrical
2001 — 2005
Skills
- Soft Skills
- Pcb Design
- High Speed Design
- Signal Integrity
- Automotive
- Schematic Capture
- Allegro
- Fpga
- Orcad
- Automotive Electronics
- Vhdl
- Cpld
- Hardware Design
- Logic Design
- Xilinx
- Pads
- Digital Electronics
- Circuit Design
- Electronics
- Digital Design
- Component Selection
- Hardware Development
- Hardware Architecture
- Analog Circuit Design
- Component Engineering
- Microcontrollers
- Integrated Circuit Design
- Design for Manufacturing
- Embedded Systems
- Analog
- Testing
- Electronic Circuit Design
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