Jon Howell

About Jon Howell

Conducting mixed signal verification of ASICs across many of Cirrus Logic\'s various…

Experience

1. Design Verification Engineer

   Cirrus Logic

   Jun 2016 — Present · Austin, TX, US

   Digital and mixed signal verification for ASICs and FPGAs used in multiple types of devices (MEMS microphones, smart amplifiers, SoundWire bridge, Codecs, Battery Protection, Battery Charging) used in mobile devices, headphones, laptops, etc. I\'ve had the opportunity to do many roles across those various projects and gather experience in multiples areas of verification. These areas include the following- Block level testbench generation, chip and system level verification, DMS simulations, AMS simulations, gate level simulations, testbench generation, and behavioral modeling. Experienced with the following tasks- SystemVerilog check generation, assertion generation, bit-accurate scoreboard generation, Matlab signal characteristics checking, meaningful functional coverage generation and collection, and code coverage management and optimization- CDC and inting tools, and error correction associated with them - Experienced with creating/modifying analog circuit behavioral models in SystemVerilog and modifying matlab models- Translating and developing testplans based on system level Matlab Simulink models Experience as a verification lead- Verification planning, requirement generation and management, peer task management, and testbench management Experience as a testbench lead- Developing and refactoring testbench architecture and testbench IP Continuous Development Of Tools- Created flow for optimizing code coverage (now deployed across company)- Created tool to show correlation between signal performance to signal characteristics graphically using regression data- Expanded graphic correlation tool to give predictive results of signal characteristics using machine learning, eliminating the need to run as many simulations.