John Dickhoff
Sr Dft Engineer @Intel
Northampton, PA, US
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Feb 2016 — Present
Sr Dft Engineer @Intel
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Flow development and execution for DFT, ATPG and related tasks for SoCs using 16nm and 10nm silicon technologies.
EDUCATION
1981 — 1984
Duke University
BSEE, Electrical Engineering and Computer Science
SKILLS
VerilogSynopsys ToolsStatic Timing AnalysisObject-Oriented ProgrammingEdaJsonLow-Power DesignMysqlSystemverilogFunctional VerificationCompilersAsicPhysical DesignXmlPrimetimePerlIntegrated Circuit DesignUbuntuAutomatic Test Pattern Generation (Atpg)AtpgPhpTimingSystem on a Chip (Soc)SimulationsLogic DesignCRtl DesignDftTclDebuggingFormal VerificationVlsiBoundary Scan Ieee 1149.1BistLynx Design EnvironmentTiming ClosureLogic SynthesisSocApplication-Specific Integrated Circuits (Asic)Javascript
ABOUT JOHN DICKHOFF
In recent teams I have focused on advancing design-for-test (DFT) methodologies for…
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