John Dickhoff
- Role
- Sr Dft Engineer at Intel
- Location
- Northampton, PA, US
- LinkedIn followers
- 500 followers
About John Dickhoff
In recent teams I have focused on advancing design-for-test (DFT) methodologies for…
Experience
Sr Dft Engineer
Feb 2016 — Present
Flow development and execution for DFT, ATPG and related tasks for SoCs using 16nm and 10nm silicon technologies.
Education
Duke University
BSEE, Electrical Engineering and Computer Science
1981 — 1984
Skills
- Verilog
- Synopsys Tools
- Static Timing Analysis
- Object-Oriented Programming
- Eda
- Json
- Low-Power Design
- Mysql
- Systemverilog
- Functional Verification
- Compilers
- Asic
- Physical Design
- Xml
- Primetime
- Perl
- Integrated Circuit Design
- Ubuntu
- Automatic Test Pattern Generation (Atpg)
- Atpg
- Php
- Timing
- System on a Chip (Soc)
- Simulations
- Logic Design
- C
- Rtl Design
- Dft
- Tcl
- Debugging
- Formal Verification
- Vlsi
- Boundary Scan Ieee 1149.1
- Bist
- Lynx Design Environment
- Timing Closure
- Logic Synthesis
- Soc
- Application-Specific Integrated Circuits (Asic)
- Javascript
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