John MacBeth
Verification Architect @Cadence
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WORK HISTORY
Verification Architect @Cadence
Edinburgh, GB
EDUCATION
University of Strathclyde
Bachelor’s Degree, Electrical and Electronic Engineering
University of Strathclyde
Doctor of Philosophy (Ph.D.), Electrical and Electronic Engineering
SKILLS
ABOUT JOHN MACBETH
Consultant for 21+ years in the area of ASIC verification and all associated technologies/methodologies. Recent focus has been on the verification of digital design IP and handling the complexity of massive configuration spaces. Often with a focus on automotive markets and so working to achieve ISO26262 compliance at ASIL-B/C range.Specialties- Verification Methodology and Theory - especially using UVM to architect constrained random verification environments for module/block level and SoC level verification - Verification Planning – Metric Driven Verification (MDV)/Coverage Driven Verification (CDV)- Verification IP (VIP) creation and support- Direct Test Management- Assertion Based Verification (ABV) using SVA- SystemVerilog - VMM/OVM/UVM (1.1.d and 1.2)- Specman e - eRM/OVM-e/UVM-e- Revision Control Management (SVN, Clearcase, P4, git)- Continuous Integration and Continuous Delivery using Jenkins-CI- FPGA Design (static and dynamic)Protocols- MIPI: CSI2, DSI- AMBA: AHB, APB3/4, AXI3/4 (lite/stream/full), CHI (C to D)- Serial protocols: USB2, USB3.x, PCIe Gen 1 to 3 (including PIPE), SDIO, UART, CPRI, Ethernet, PROFINET- Other bus protocols: OCP- Other: LTE/LTE-A Programming Languages/scripts/RTL- SystemVerilog, Verilog, VHDL- SystemC, Specman e- C (for general programming and for embedded SW)- C++, Java- Perl, Python, Bash, Tcl- ASM for several processor architectures - focus on embedded SW development and very low level testing - GNU Make
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