John Fisher

About John Fisher

Led and worked on mixed-signal design teams to fabricate over 100 designs and to gain 20 years of industry experience, in addition to project based academic experience.• Over 12 years of management experience developing team members, leads, and managers• Led project teams to consistently complete and release designs on projected and aggressive schedules, for full DDR PHY custom IP and high speed ADC product lines.• Specified, modeled, simulated, and implemented DDR IO receiver and clock distribution, analog-to-digital converters (including flash, pipelined, Delta-Sigma Modulator, and successive approximation types), digital-to-analog converters, comparators, operational amplifiers, bandgap references, sample-and-hold circuits, track-and-hold circuits, bias current and voltage generators, programmable gain amplifiers, voltage and current buffers.• Specialties: Proficient with Cadence tools for schematic capture (Composer), simulation (ADE, OCEAN, Spectre, SpectreRF, AMS, NCSIM), layout (Virtuoso), and verification (DRC, LVS, QRC), Synopsys CC tools, Andromeda and SGE load balancing, Matlab, Verilog-AMS, Laytools, Magic, Spicecad, Berkeley Spice, HSpice, TopSpice, Maple, octave, and Microsoft Office tools• Programmed/scripted in PERL, SKILL, c-shell, bash, TCL, C++/C, python, assembler, microcode• Ensured team achieved ISO 9001 certification, including project and data management requirements• Training courses in communication, management, teamwork, stress, and engineering ethics

Experience

1. Analog Mixed-signal Ic Design Manager

   Synopsys Inc

   Sep 2014 — Present · Boxborugh, MA, US

   Managed multi-site team of analog/mixed-signal IC managers, designer, and layout engineers• Mentored development of new front line managers, project leads, and designers• Developed technical feasibility analysis for road map planning for 7nm and 5nm technology nodes, as well as project resourcing planning for custom circuit design efforts and custom design quotes• Led new platform development of custom IP for 7nm DDR5/DDR4 PHY with a strategy of ensuring acceptable designs were consistently in place to meeting program goals, and evaluation in parallel of other design options for improved performance and porting, including leading effort to port for 14nm and for first Synopsys 5nm DDR IP• Led initial LPDDR4X feature addition to existing custom IP blocks of DDR43/LPDDR4 PHY and executed 16nm and 7nm designs on aggressive schedule, prioritizing schedule and balancing likely risk factor• Led team to develop custom IP blocks of both 7nm and 10nm DDR4/LPDDR4 PHY, on highly controlled schedule with excellent design coverage and pre-fetching of customer needs• Led initial design development of custom IP blocks for 14nm HBM2 PHY• Led customer support efforts for R&D team, with key focus on responsiveness to customer schedule• Led development of custom IP checking flow for customer releases, including development of release depot structure, standard design checks, custom scripts, and layout sign-off checklists from porting specification

Education

• The Ohio State University

  Doctor of Philosophy (Ph.D.), Electrical and Electronics Engineering

  1999 — 2006

• The Ohio State University

  Master's degree, Electrical and Electronics Engineering

  1997 — 1999

Skills

• Opamp
• Mixed Signal
• Analog
• Ic
• Cmos
• Analog Circuit Design
• Semiconductors
• Pll
• Spectre
• Dac
• Serdes