Joe Sargunaraj
Principal Performance Architect at AMD
- Role
- Principal Performance Architect at AMD
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Joe Sargunaraj
Experienced in verifying CPU Data Fabric, Components of storage bridge/routers, IP edge router and Server/Workstation chipsets. Experienced in early adoption of evolving verification methodologies in the industry including SystemVerilog/OVM and C++ to verify complex SoC designsManaged large and geographically distributed verification teamsSpecialties: Design Verification and Managing Verification teams
Experience
Principal Performance Architect
Feb 2018 — Present · San Francisco, CA, US
Memory Subsystem performance architecture
Education
Anna University Chennai
B.E., Electrical & Electronics Engg
1992 — 1996
Villanova University
Master of Science (M.S.), Electrical Engineering
1996 — 1998
Skills
- Dft
- Shell Scripting
- Power Management
- Rtl Design
- C++
- Processors
- Perl
- Vlsi
- Asic
- Debugging
- Soc
- Static Timing Analysis
- Systemverilog
- Simulations
- Ovm
- Verilog
- Rtl Coding
- C
- Project Planning
- Linux
- Open Verification Methodology
- Firmware
- Functional Verification
- Semiconductors
- Low-Power Design
- Arm
- Hardware Architecture
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