Jithin Ratheesan
Engineering on Silicon
- Role
- Analog Design Manager at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jithin Ratheesan
Design Engineer Timing and Methodology Development.(MSIP/STDCELLS)
Experience
Analog Design Manager
Feb 2025 — Present · IN
Education
Cochin University of Science and Technology
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
2008 — 2012
Amrita School of Engineering Coimbatore
Master of Technology (MTech), VLSI Design
2013 — 2015
Skills
- Cadence Icfb
- C++
- Cadence Virtuoso
- Very-Large-Scale Integration (Vlsi)
- Mentor Graphics
- Altera Quartus
- Xilinx
- C
- Programming
- Matlab
- Microsoft Office
- Vlsi
- Core Java
- Hspice
- Python
- Fpga
- Microsoft Excel
- Powerpoint
- Cadence Liberate
- Ajax
- Standard Cell
- Verilog
- Primetime
- Microsoft Word
- Field-Programmable Gate Arrays (Fpga)
- Perl Automation
- Vhdl
- Xilinx Ise
- Embedded Systems
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