Jitendra Kushwaha
Sr Director SoC Engineering | GPU | AI | HPC | UVM | System Verilog| PCIe| DisplayPort |MIPI
- Role
- Sr Director Soc Engineering at Synopsys Inc
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Jitendra Kushwaha
Design Verification, Universal Verification Methodology(UVM), System Verilog, Verification IPs, SoC Verification, Verification Lead, Program management. Japanese languageTechnologies: DisplayPort, HDMI, Camera Engine, MIPI soundwire/CSI/DSI/UniPro, AMBA AHB/APB, USB 3.0,CXL
Experience
Sr Director Soc Engineering
Aug 2024 — Present · Folsom, CA, US
Education
Georgia College & State University
Master of Business Administration (M.B.A.), Business Administration and Management, General
2014 — 2016
Japan educational exchanges and services
N2 Level, Japanese Language
2010 — 2010
Harcourt Butler Technical University
Bachelor's degree, Electrical and Electronics Engineering
1997 — 2001
Skills
- Verilog
- Digital Hardware Design
- Functional Verification
- Wafer Testing
- Video Procesing Chip Design
- Display Driver Ic Deisgn & Verification
- Asic
- Ic
- Systemverilog
- Testing
- Mipi Soundwire
- Integrated Circuit Design
- Digital Electronics
- Debugging
- Digital Signal Processors
- Soc
- Application-Specific Integrated Circuits (Asic)
- Integrated Circuits (Ic)
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