Jitendra Aggarwal

About Jitendra Aggarwal

Shift-left << HWAccel << Pre-Silicon << Silicon * Vast experience in driving SoC/IP Verification and Validation lifecycles* Technically well-versed with front-end validation methodologies like UVM, SVA, Coverage, Low Power, Power estimation, DFT, Fault Injection* Specialised in setting up verification environment from scratch and taking it to its advanced optimum usage* Worked as a primary interface in various geographies with clients - Intel, Samsung, ST, Microsoft, AMD, Broadcom, Avago, Qualcomm, Xilinx, Cypress, Juniper, SK Hynix* Experience includes various roles in Solutions and Methodology Innovation, Engineering Management, Technical Pre-Sales evaluations and Post-Sales support.

Experience

1. Senior Director of Engineering

   新思科技股份有限公司

   Dec 2025 — Present

   HPC, Automotive and Client focused IO and Memory Chiplets to accelerate ASIC/Systems lifecycle using Synopsys+Ansys product portfolio around IO, EDA and simulation analysis

Skills

• Soc
• Low-Power Design
• Systemverilog
• Emulation
• Vlsi
• Debugging
• Pcie
• Fpga
• Asic
• Verilog
• Vhdl
• Simulations
• Perl
• Embedded Systems
• Eda
• Linux
• System on a Chip (Soc)
• Unix
• Tcl