Jitendra Mishra
AMS Engineer
- Role
- Ams Design & Verification Engineer at 恩智浦半导体
- Location
- Kanpur Nagar, UP, IN
- LinkedIn followers
- 500 followers
About Jitendra Mishra
Experience in AMS verification flow and methodology, development of verification plan and test cases as per targeted analog IPs for SOC, regress analysis and debug. Also, experience in analysis and verification of various analog block of high speed SerDes system like CTLE, clock division circuit, pre driver etc. for PCIe.
Experience
Ams Design & Verification Engineer
Oct 2022 — Present · Noida, IN
Education
National Institute of Technology Silchar
Master of Technology (M.Tech.), Microelectronics & VLSI Design
Indian Institute Of Information Technology Allahabad
Doctor of Philosophy (PhD), Microelectronics & VlSI Design
Skills
- Vlsi Cad
- Microsoft Office
- Vlsi
- Matlab
- Cmos
- Research
- Silvaco
- Vhdl
- Vhdl-Ams
- Cadence Virtuso
- Verilog
- Design and Simulation of Analog and Digital Circuits
- Xilinx Ise
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