Jitendra Jha
Chiplet Integration engineer at Intel
- Role
- Chiplet Integration Engineer at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Jitendra Jha
As Chiplet Integration Engineer (3D Packaging Technology), I have been leading 3D packaging manufacturing efficiency improvement program at Intel.As process Integration engineer, I was leading front-end mid-section development of latest Intel technology node manufacturing.
Experience
Chiplet Integration Engineer
Jul 2023 — Present · Hillsboro, OR, US
Program leader of chiplet integration (3D packaging technology) manufacturing efficiency improvement project.
Education
National Institute of Technology Raipur
Bachelor of Technology (B.Tech.), Metallurgical Engineering
2006 — 2010
Rose Public School
Senior Secondary, High School/Secondary Certificate Programs
1997 — 2005
University of North Texas
Doctor of Philosophy (Ph.D.), Material Science and Engineering
2012 — 2016
Skills
- Powder X-Ray Diffraction
- Sputtering
- Engineering
- Research
- Thermal Evaporation
- Ultraviolet Photoelectron Spectroscopy
- Thin Films
- Materials Science
- Pulsed Laser Deposition
- Optical Microscopy
- Data Analysis
- Metallurgy
- Electroluminescence
- Hall Measurement
- Nanotechnology
- X-Ray Photoelectron Spectroscopy
- Xps
- Scanning Electron Microscopy
- Tem
- C++
- Afm
- C
- Microsoft Office
- Photoluminescence
- Ellipsometry
- Raman Spectroscopy
- Characterization
- Spectroscopy
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