Jinia Biswas
Staff Engineer at Samsung SemiconductorIndia Research || Physical Design Engineer
- Role
- Staff Engineer at Samsung Semiconductor
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Jinia Biswas
Relevant experience of 6 +years in Physical Design. Responsible for physical implementation of a block – starting from netlist to gds, including Floor planning, placement optimization, clock tree synthesis, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis and eco fixing. Worked on unconstrained paths debugging. Hands on Experience in Synopsys ICC2, Prime time, Calibre, Redhawk,Fusion compiler, IC Validator. Worked on multiple Technology nodes: TSMC 16nm FinFet, INTEL 10 nm,Intel 3 nm, INTEL 16 nm. Generated timing setup/hold ECOs, leakage ECO, trans fix ECO using Primetime for block level implementation for block closure. Hands-on experience on STA, LEC, DRC-LVS, Antenna fixing. EM-IR analysis, debugging and closure. Ability to work independently as well as excellent collaboration and teamwork with other physical design engineers and Design team.
Experience
Staff Engineer
Nov 2023 — Present · Bengaluru, IN
Education
Regent Education and Research Foundation Group of Institutions
Bachelor of Technology - BTech
2009 — 2013
Skills
- Vhdl
- Verilog
- Microsoft Excel
- Powerpoint
- Microsoft Powerpoint
- C
- Microsoft Office
- Html
- Linux
- Cmos
- Design Rule Checking (Drc)
- Layout Design
- Lvs
- Layout Versus Schematic (Lvs)
- C++
- Matlab
- Drc
- Windows
- Sram
- Cadence Virtuoso
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