Jingliang Wang
Verification Tech Lead
- Role
- Verification Tech Lead at Akeana
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
Experience
Verification Tech Lead
Mar 2021 — Present · Austin, TX, US
After leaving Futurewei, I had joined Cadence Design Systems already. But my previous manager/coworkers called me for an exciting startup they are planning on. I had to say sorry to Cadence after being there one month and jointed this stealth mode startup.The work here is challenging, we are doing seemly impossible things, but I really like being in this kind of environment.
Education
Tsinghua University
Bachelor, Automatic Control
1991 — 1996
Michigan State University
Master, Computer Engineering
1999 — 2001
Skills
- Debugging
- Systemverilog
- Arm Architecture
- Memory System Verification
- Processors
- Multiprocessing Verification
- C++
- Perl
- Soc
- Rtl Design
- Python
- Mips Architecture
- Functional Verification
- Powerpc
- Random Test Generator
- Integrated Circuit Design
- Semiconductors
- X86
- Power Architecture
- Verilog
- Arm
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