Jing Miao
- Role
- Test Engineer at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
Experience
Test Engineer
Apr 2017 — Present
Skills
- Rf & Microwave Design
- C
- Verilog
- Semiconductors
- Awr Microwave Office
- Microsoft Office
- Cadence
- Pcb Design
- Vhdl
- Synopsys Tools
- Electrical Engineering
- Testing
- Antennas
- Cadence Spectre
- Modelsim
- Labview
- Electronics
- Awr-Mwo, Axiem
- Cadence Virtuoso Layout Editor
- Xilinx Ise
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