Jing Gao
ASIC Design Engineer at Google TPU team
- Role
- Asic Design Engineer at Google
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jing Gao
Hands-on experience in AI accelerator and GPU design
Experience
Asic Design Engineer
Apr 2025 — Present
ASIC Design Engineer at Google TPU team
Education
The Hong Kong Polytechnic University
Bachelor of Science (BS), Engineering Physics/Applied Physics
2009 — 2013
University of Michigan
Master of Science (MS), Electrical and Computer Engineering, VLSI
2013 — 2015
Skills
- Vlsi
- Cadence
- C++
- Sql
- Oracle Sql Developer
- Cmos
- Verilog
- Ic
- Semiconductor Device
- Physics
- Circuit Design
- Computer Architecture
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