Jin Yu
Wafer Fab Engineer at Texas Instruments
- Role
- Wafer Fab Engineer at Texas Instruments
- Location
- Dallas-Fort Worth, TX, US
- LinkedIn followers
- 500 followers
About Jin Yu
20+ years of experience in semiconductor photolithography related fields; of which 13…
Experience
Wafer Fab Engineer
Dec 2009 — Present · Dallas-Fort Worth, TX, US
Photo I-line Metal/TIN/HVCTOP/TFHEAD levels owner, excellent in performing relevant SPC, rework reduction, defect reduction, parametric and multi-probe yield improvements; Photo QC story & Process Yield champion; ALBEOL DFT/QTS (QA customer return) – Photo Representative; Hitachi CD SEM process tool owner or back-up; Visual inspection process tool ownerWEE (Wafer Edge Exposure) reduction for DUV Metals Patterning. Published this innovation in the company Yield Conference. Rework reduction for i-line metal / HVCTOP patterning through alignment marks improvements
Education
University of Chinese Academy of Sciences
Ph.D in Engineering
Skills
- Spc
- Semiconductors
- Process Simulation
- Start-Ups
- Testing
- Metrology
- Jmp
- Characterization
- Photolithography
- Yield
- Materials
- Analysis
- Engineering
- Lithography
- Powder X-Ray Diffraction
- Thin Films
- Process Improvement
- Optics
- Project Management
- Data Collection
- Troubleshooting
- Design of Experiments
- Manufacturing
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