Jimmy Storie

About Jimmy Storie

14 nm through 180 nm. Floorplan to tapeout. Low power SOI and High Voltage. M GHZ up to…

Experience

1. Rfic Mixed Signal Layout Engineer

   Agilent Technologies

   Jun 2010 — Present

   Third time at Agilent (as a contractor), totaling 4 years.RFIC Layout Designer, Agilent Technologies, Santa Clara Layout of analog and custom digital circuits for very high speed ADC and Serial Transceiver chips in BiCMOS (130 nm CMOS + 165 GHz bipolar, 7-layer metal, flip-chip). Worked closely with engineers to meet demanding requirements for low capacitance, good matching, electromigration, noise suppression and isolation, supply drops, density and global layout fit. Worked on: ECL logic gates and buffers, custom CMOS logic gates and buffers, low-jitter clock chains, DACs, high-power buffers, track-and-hold circuits, comparators, transmission-line wiring channels. Worked from transistor level to the major-block level of the chip. Used Cadence Virtuoso-XL and Mentor Calibre

Skills

• Integrated Circuit Design
• Lvs
• Cadence
• Ic
• Analog
• Mixed Signal
• Floorplanning
• Rfic
• Bicmos
• Physical Verification
• Rfic
• Analog Circuit Design
• Semiconductors
• Drc
• Cmos
• Asic
• Simulations
• Layout Versus Schematic (Lvs)
• Digital Electronics
• Eda
• Cadence Virtuoso