Jimit Shah

Experience

1. Sr Staff Engineer

   Qualcomm

   Dec 2021 — Present · Bengaluru, IN

   Working on uArch and HW design for DDR sub systemInvolved in command flow development, area and what-if analysis for different IPsWorking on the Last Level Cache controller

Education

• University of Mumbai

  BE, Electronics

  2003 — 2006

• Indian Institute of Science (IISc)

  Mtech, Electronics Design and Studies

  2006 — 2008

• Rajhans Vidhyalaya

  SSC

  1989 — 1999

• Shri Bhagubhai Mafatlal Polytechnic

  Diploma, Industrial Electronics

  1999 — 2003

• Sardar Patel College of Enggineering

  Bachelor of Engg, Electronics

  2003 — 2006

Skills

• Tcl
• Rtl Design
• Arm Architecture
• Timing Closure
• Fpga
• Asic
• Vlsi
• System on a Chip (Soc)
• Field-Programmable Gate Arrays (Fpga)
• Debugging
• Pcie
• Application-Specific Integrated Circuits (Asic)
• Vhdl
• Systemverilog
• Processors
• Verilog
• Asic Design
• Integrated Circuit Design
• Functional Verification
• Soc
• Static Timing Analysis
• Vmm
• Low-Power Design
• Arm
• Uvm
• Serdes
• Eda