Jihong Choi
Principal Engineer Manager @高通
San Diego County, CA, US
EMAILS
j••••••@qti.qualcomm.com
MOBILE NUMBERS
+15•••••••95
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WORK HISTORY
Jan 2012 — Present
Principal Engineer Manager @高通
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San Diego, CA, US
Process and package solutions- Custom high BW DRAM solutions- 3D DRAM, STCO, DTCO- Chiplet and heterogeneous integration, 2.5D, 3DIC development- IPD, passive device development- Advanced process technology and foundry engineering- Foundry NPI and yield ramp
EDUCATION
N/A
Yonsei University
BS, Mechanical Engineering
N/A
University of California, Berkeley
Ph.D., Mechanical Engineering
N/A
University of California, Berkeley
M.S., Mechanical Engineering
SKILLS
Layout ToolsTestingDfmDrcMatlabSiliconPhysical VerificationDevice PhysicsSimulationsSemiconductor ManufacturingSemiconductorsDoeC++Design for ManufacturingTclMemsCmosEdaIcJmpFinite Element AnalysisFailure AnalysisSemiconductor Design RulesDesign of ExperimentsManufacturingProcess IntegrationThin Films
ABOUT JIHONG CHOI
Principal engineer /Manager at Qualcomm
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