Jignesh B
Staff Engineer @ Qualcomm | Expert in Static Timings Analysis
- Role
- Staff Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Jignesh B
8+ Years of work Experience in STA | Worked on 25+ SOC | Lead STA signoff engineer for 15+ sub systems.As a staff engineer at Qualcomm, I apply my M.Tech. degree in VLSI and embedded systems and my skills in low-power ASIC design to create and optimize chips for various products and platforms for timings Signoff. I have a strong understanding of the core technology and the industry standards, and I work with a talented and diverse team of engineers to deliver innovative and reliable solutions.STA lead for 5G modem chips and DDR SS, I have successfully closed timing for full flat modem designs/DDR subsystems in tech nodes ranging from 11nm to 4nm. I have also navigated critical challenges in performance, power, and area tradeoffs, and received recognition from senior managers and cross-site engineers for my commitment and velocity in executions. I am passionate about learning new technologies and exploring new challenges in the field of VLSI and ASIC design.
Experience
Staff Engineer
Nov 2024 — Present · Bengaluru, IN
Education
Dr. Subhash University
Bachelor of Technology (B.Tech.), ECE
2010 — 2014
Dhirubhai Ambani University
Master of Technology (M.Tech.), VLSI and Embedded System
2015 — 2017
Navyug School, Vadodara, Gujarat
Matriculation, Science
2007 — 2008
M.G.M. School, Vadodara, Gujarat
Intermediate/+2, PCM
2009 — 2010
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