Jigar P.
20+ ASIC Verification Engineer
- Role
- Principal Engineer at Analog Devices
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jigar P.
ASIC Verification 19+ exp,Expert in SV based verificationSpecialties: Verification using System Verilog, UVM, Soc,Subsystem,IP level verification, execution from scratch
Experience
Principal Engineer
Mar 2023 — Present
Education
Griffith University
M.E., MEMS Design/ VLSI
2003 — 2004
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