Jibin Cheriyan

About Jibin Cheriyan

Experience in technology nodes 45nm, 28nm and 22nm,16nm, 5nm, 3nmHandled Top-level and block level netlist to gdsii implementationLow power design with UPF.Expertise in Toplevel Floor Planning,Power planning, Placement & Optimization, Clock Tree Synthesis, Routing, ECO steps,Timing Closure,XTALK- SI Analysis, DRC/LVS, LEC.Exposure to Lower power design techniques, IR drop analysis, multi power design, Level shifters, Isolation cells & OCV.Skill Sets• Top level floorplan, partitioning,placement and CTS and managing block status and it\'s closure.• Top level timing, interface timing.• Block level floorplan and powerplan• Place and Route• Clock tree synthesis• Timing closure• DRC, and LVS verification• STA • Formal Verification • Scripting in TCL, Perl & Shell.Tools• PnR Tools : Synopsis IC compiler, Encounter/Innovus and Talus Magma• STA Signoff : Synopsis PrimeTime, Tempus• Power Analysis : Apache Redhawk• RC Extraction : Star RC/Qrc • DRC Signoff : Calibre, Hercules

Experience

1. Sr Physical Design Engineer

   Google

   Jul 2023 — Present · Bengaluru, IN

Education

• MES College of Engineering, Kuttippuram

  Bachelor of Technology - BTech, Electronics and Communications Engineering

• Indian Institute of Management, Kozhikode

  Advanced Management Programme, Management

• Indian Institute of Science (IISc)

  Advanced Programme, VLSI Chip Design

Skills

• Clock Tree Synthesis
• Physical Design Pnr
• Power Analysis
• Static Timing Analysis
• Tcl
• Application-Specific Integrated Circuits (Asic)
• Physical Verification
• Soc
• Formal Verification
• Lvs
• Asic
• Cadence Tempus
• Layout Versus Schematic (Lvs)
• Timing Closure
• Perl
• System on a Chip (Soc)
• Redhawk
• Synopsys Ic Compiler
• Cadence Encounter
• Place & Route
• Low-Power Design
• Design Rule Checking (Drc)
• Drc
• Primetime