Jiayou Wei
- Role
- Design Verification Engineer at Synapse Design Inc
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jiayou Wei
Currently looking for full time job in ASIC/SOC design or verification. 1)In depth…
Experience
Design Verification Engineer
Sep 2021 — Present
Skills
- Tcl
- Cadence Virtuoso
- Synopsys Design Compiler
- C
- Linux
- Pcb Design
- Algorithm
- Cadence Nc-Verilog
- Verilog
- Perl
- Computer Architecture
- Matlab
- C++
- Hspice
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