Jiawei Zhang

About Jiawei Zhang

Hand-on experience in IC package co-design flow (Die/Package/System). Experience in advanced package, FCBGA, MCM, SiP. Aid Apache Sentinel PSI/NPE Chip-Package-System Co-Design/Co-analysis Suite for package SI/PI performance. Proficient in Cadence APD, hand on electronic packaging products. Optimized package layout, die floorplan, I/O pad order and bump level I/O assignment to achieve performance target for system level. New packaging development (new material, high frequency signal, yield and low cost). Proficient in Cadence APD, hand on electronic packaging products. Proficient in full line of advanced assembly equipments, analytical equipment, reliability testers. Experienced in coordinate SubCon for high volume production.

Experience

1. Principal Engineer (Ic Packaging Design and Architecture)

   Qualcomm

   Mar 2021 — Present · Santa Clara, CA, US

   Advanced IC package for HPC/data center/AI applications, future HPC Platform Technology, 3DIC, Thin Film. 2.5D with RDL bridge and DTC. 2.5D with Si-bridge and DTC. EMIB-T for chiplets.Pathfinding activities with new programs that optimize the system-level solution.(HPC).Working closely with internal and external customer partners on silicon-disaggregation and other chiplet strategies for advanced packages, including emerging-memory chiplet integration.Identifying critical elements for HPC packaging roadmap and DFM, substrate, NPI co-optmization.Driving design strategies for performance and manufacturability in packaging with Customer ASICPackage architecture for ultra-high-speed interfaces (PAM4) End-to-end IC packaging development for advanced packaging Die-package-board co-design for switches, and PHYs Close collaboration with hyperscalers, TSMC, and top OSATs

Education

• Auburn University

  PhD, Systems Engineering

  2009 — 2012

• Auburn University

  Master, Electrical and Computer Engineering

  2007 — 2009

• Beihang University

  Bachelor, Electrical and Computer Engineering

  2002 — 2006