Jiawei Tao
- Role
- Asic Design Engineer at Ambarella Inc
- Location
- Sunnyvale, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jiawei Tao
Strengths include more than 3 years’ experience in RTL design; Proficiency with Verilog…
Experience
Asic Design Engineer
Sep 2018 — Present
Skills
- Simulink
- Primetime
- System C
- Questasim
- Verdi
- Perl
- Linux
- Tcl
- Systemverilog
- Matlab
- Ncsim
- Python
- Fpga
- Modelsim
- C++
- Lec
- Verilog
- Encounter
- Cadence Virtuoso
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