Xueying Jiang
VLSI Physical Design @Nvidia | Ex-Cadence | USC
- Role
- Physical Design Engineer at NVIDIA
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Physical Design Engineer
Feb 2022 — Present · Santa Clara, CA, US
Education
North China University of Technology
Bachelor of Science (BS)
2009 — 2013
University of Southern California
Master's Degree
2013 — 2015
Skills
- Fpga
- Asic
- Tetramax Atpg
- Java
- Modelsim
- Cadence Virtuoso
- Perl
- Systemverilog
- C
- Vlsi
- Verilog
- Systemc
- Xilinx Ise
- Vhdl
- Matlab
- Dc
- Ius
- Algorithms
- Primetime
- C++
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