Jianfeng Lisa Wang
Device Engineer with module experience | FinFet GAA Si CMOS/vertical GaN power devices/III-N LEDs
- Role
- Device Engineer at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Jianfeng Lisa Wang
Product development and device engineer with Ph.D. in electrical and optical materials and devices and 5+ years’ experience driving performance/yield/reliability ramp, product qualification, and silicon debug across advanced logic and power technologies. Proven ability to execute DOE, automate test data analysis, and lead cross-functional teams to resolve complex issues. Hands-on expertise in NPI, SPC/CPK, ATE data analysis, and product transfer from R&D to HVM. Strong communicator with track record of delivering solutions under accelerated timelines. Fluent in in English and Mandarin.
Experience
Device Engineer
Apr 2024 — Present · Hillsboro, OR, US
Developed and qualified new processes that improved product performance, yield and reliability as well as reducing defects and variation• Front end of line (FEOL) device owner for Fin and Isolation segments of Intel 3/4nm and 14A logic nodes• Led 40+ engineers to establish etest package for new product introductions (NPI) and evaluate NPI healthiness• Resolved plasma induced damage (PID) reliability risks and relaxed restrictive design rules by deep diving into etest/process interaction, device physics, and layout design • Designed front-end isolation test structures to enhance yield analysis using Cadence Virtuoso
Education
UC Santa Barbara
Doctorate, Materials Science
2015 — 2020
Penn State University
Other, Economics
2013 — 2015
Penn State University
Bachelor's Degree, Materials Science and Engineering
2013 — 2015
Harbin Institute of Technology
Bachelor's Degree, Advanced Welding and Joining
Skills
- Glove Box
- Optical Microscopy
- C++
- C Language
- Microsoft Office
- Matlab
- Crystal Maker
- Materials Studio
- Sketching
- Guzheng
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