Jian Qiao
ASIC Design, Architect
- Role
- Senior Silicon Engineer at 微软
- Location
- San Diego, CA, US
- LinkedIn followers
- 500 followers
About Jian Qiao
As a Sr. staff engineer, I have been working 11+ years in ASIC design area. My specialties includes wireless 5G RF and baseband chipset digital design, High speed data transfer protocol like PCIe and etc, image and video processing AI accelerator, RISC-V edge cpu and solid state drive controller. I\'m experienced in architecture, system, micro-architecture and RTL design, hands on experience in full design flow (lint/CDC/RDC/Synthesis/STA). I have contributed to multiple successful projects and completed multiple production level silicon tape outs. I am confident in my ability to deliver high-quality designs that meet or exceed project requirements.
Experience
Senior Silicon Engineer
Jul 2023 — Present · San Diego, CA, US
Education
Beijing University of Posts and Telecommunications
BS, telecommunication engineering
2006 — 2010
University of Southern California
Master’s Degree, Electrical and Electronics Engineering
2010 — 2011
Skills
- Ufs
- Vhdl
- Otp
- Xilinx
- Sata
- Atpg
- Integrated Circuit Design
- Verilog
- Eco
- C
- Vlsi
- Modelsim
- Primetime
- Unix
- Soc
- Rtl Design
- Dft
- Low Poly Modeling
- Xilinx Ise
- C++
- Static Timing Analysis
- Formal Verification
- Object Oriented Software
- Sas
- Circuit Design
- Cadence Virtuoso
- Computer Architecture
- Logic Design
- Scripting
- Java
- Functional Verification
- Jtag
- Axi
- Perl
- Fpga
- Pcie
- Asic
- Bist
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