Jheel Nagaria

About Jheel Nagaria

Experienced Electrical Engineer with a Master\'s degree focused in Electrical Engineering (VLSI Design) from University of Southern California. Trained in Post-Silicon and Pre-Silicon Validation of Qualcomm\'s next generation Mobile Compute Chips. Worked on LPDDR5 and LPDDR5X memory interfacing and tuning with Snapdragon SoC. Carried out Timing Analysis, Signal Integrity Power Integrity (SIPI) Analysis and QA on Training Algorithms for Snapdragon 8+ Gen 1 bring-up. Developed Drivers and test cases in C and Trace32 cmm scripts for quick software enablement. Integral part of critical silicon/hardware debugs leading to software work-arounds

Experience

1. Senior Engineer

   高通

   Jan 2022 — Present · San Diego, CA, US

   Trained in Post-Silicon and Pre-Silicon Validation of Qualcomm\'s next generation Mobile Compute Chips• Worked on LPDDR5 and LPDDR5X memory interfacing and tuning with Snapdragon SoC• Carried out Timing Analysis, Signal Integrity Power Integrity (SIPI) Analysis and QA on Training Algorithms for Snapdragon 8+ Gen 1 bring-up• Developed Drivers and test cases in C and Trace32 cmm scripts for quick software enablement• Integral part of critical silicon/hardware debugs leading to software work-arounds

Education

• University of Southern California

  Master’s of Science (MS), Electrical Engineering

• Ramnarain Ruia College - Mumbai

  Higher Secondary Education, Mathematics, Physics, Chemistry, Electronics

  2012 — 2014

• Veermata Jijabai Technological Institute (VJTI)

  Bachelor of Technology (B. Tech), Electronics Engineering

  2014 — 2018