Jeyakumar A

About Jeyakumar A

Experience in Verilog RTL based IP design, simulation, synthesis and verification• Experience in SOC integration• Experience in AMBA/I2C bus protocols, MIPI, SD/MMC protocols.• Synthesis of FPGA/ASIC designs• Gate level netlist and timing simulations• Functional pattern generation and re-simulation• FPGA/Post silicon validation • DC/RC synthesis scripts• LINT checks• Advance CDC checks• Non-Resettable flop checks• RMM guidelines and synthesis techniques• Verilog behavioral modelingSpecialties: Tools-Simulation - ModelSim, NC Sim, VCS, NC-Verilog and Aldec’s Active HDL, Synthesis - Design Compiler, RTL Compiler, Leonardo Spectrum, Synplify Pro and Quartus, Lint - VNCHECK and SpyGlassAdvanced CDC - 0-In CDCNon-Resettable flops - Jasper

Experience

1. Sr Staff Engineer Mgr

   Qualcomm

   Dec 2018 — Present · Bengaluru, IN

Education

• Madurai Kamaraj University

  B.E, Electronics and Communication Engineering

  1999 — 2003

• St.Thomas Matriculation Higher Secondary School

  SSLC, Matric Board

  1989 — 1997

• I.R.T Polytechnic Tirunelveli

  Diploma, Electronics and Communication Engineering

  1997 — 2000

Skills

• Verilog/Vhdl Design, Verification, Synthesis Training
• Modelsim
• Verilog Design/Simulation
• Logic Synthesis
• Vhdl
• Lint
• Lint,Cdc, Rmm Checks
• Vlsi
• Verilog
• Fpga/Asic Synthesis
• Fpga/Asic Validation
• Ncsim
• Rtl Coding
• Checks
• Functional Verification
• Verilog Based Behavioral Modeling/Verification